A Group-Theoretic Model for Symmetric Interconnection Networks
IEEE Transactions on Computers
Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.)
Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.)
The Organization of Permutation Architectures with Bused Interconnections
IEEE Transactions on Computers
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
On the Complexity of Optimal Bused Interconnections
IEEE Transactions on Computers
Bused Hypercubes and Other Pin-Optimal Networks
IEEE Transactions on Parallel and Distributed Systems
Exact Bounds on Running ASCEND/DESCEND and FAN-IN Algorithms on Synchronous Multiple Bus Networks
IEEE Transactions on Parallel and Distributed Systems
On the Complexity of Optimal Bused Interconnections
IEEE Transactions on Computers
Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms
IEEE Transactions on Computers
Routing Algorithms on the Bus-Based Hypercube Network
IEEE Transactions on Parallel and Distributed Systems
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We develop a formal and systematic methodology for designing an optimal multiple bus system (MBS) realizing a set of interconnection functions whose graphical representation (denoted as IFG) is symmetric. The problem of constructing an optimal MBS for a given IFG is NP-Hard. In this paper, we show that polynomial time solutions exist when the IFG is vertex symmetric. This is the case of interest for the vast majority of important interconnection function sets.We present a particular partition (which can be found in polynomial time) on the edge set of a vertex symmetric IFG, that produces a symmetric MBS with minimum number of buses as well as minimum number of interfaces. We demonstrate several advantages of such an MBS over a direct-link architecture realizing the same IFG, in terms of the number of ports per processor, number of neighbors per processors, and the diameter.