Co-synthesis of hardware and software for digital embedded systems
Co-synthesis of hardware and software for digital embedded systems
Real-time multi-tasking in software synthesis for information processing systems
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Thread-based software synthesis for embedded system design
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An integrated hardware-software cosimulation environment with automated interface generation
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Programming challenges in network processor deployment
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
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Latency tolerance is one of main problems of software synthesis in the design of hardware-software mixed systems. This paper presents a methodology for speeding up systems through latency tolerance which is obtained by decomposition of tasks and generation of an efficient scheduler. The task decomposition process focuses on the dependency analysis of system i/o operations. Scheduling of the decomposed tasks is performed in a mixed static and dynamic fashion. Experimental results show the significance of our approach.