On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
IEEE Transactions on Computers
On the implementation of reed-solomon decoders
On the implementation of reed-solomon decoders
Algorithms and architectures for error correcting codes (decoding, reed-solomon)
Algorithms and architectures for error correcting codes (decoding, reed-solomon)
Universal Reed-Solomon decoders based on the Berlekamp-Massey algorithm
Proceedings of the 14th ACM Great Lakes symposium on VLSI
| Hi-index | 14.98 |
A new cellular structure for a versatile Reed-Solomon (RS) decoder is introduced based on time domain decoding algorithm. The time domain decoding algorithm is restructured to be suitable for introducing the cellular structure. The main advantages of this structure are its versatility and very simple cellular structure. By versatile decoder we mean a decoder that can be programmed to decode any (n, k) RS code defined in Galois field 2m with a fixed block length n and a fixed symbol size m. This decoder can correct both errors and erasures for any message length k. The introduced decoder is cellular and has a very simple structure and hence it is suitable for VLSI designs.