Practical aspects and experiences Scalable massively parallel algorithms for computational nanoelectronics

Authors:
Xiaodong Wang;Vwani P. Roychowdhury;Pratheep Balasingam
Affiliations:
Department of Electrical Engineering, Princeton University, Princeton, NJ 08540, USA;Electrical Engineering Department, University of California, Los Angeles, Los Angeles, CA 90095-1594, USA;Meta-Software Inc., 1300 White Oaks Road, Cambell, CA 95008, USA
Venue:
Parallel Computing
Year:
1997

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Abstract

There is at present a worldwide effort to overcome the technological barriers to nanoelectronics. Microscopic simulation can significantly enhance our understanding of the physics of nanoscale structures, and constitutes a valuable tool for designing nanoelectronic functional devices. In nanodevices, novel physics effects are used to attain logic functionality which conventional technology can not achieve. Therefore it is necessary to develop quantum-transport simulation methods which include novel physical effects. Moreover, simulation of realistic nanodevices require enormous computing resource, necessitating parallel supercomputing. In this paper, we present massively parallel algorithms for simulating large-scale nanoelectronic networks based on the single-electron tunneling effect, which is arguably the quantum effect of greatest significance to nanoelectronic technology. A MIMD implementation of our simulation algorithm is carried out on a 64-processor nCUBE 2, and a SIMD implementation is carried out on a 16,384-processor MasPar MP-1. By exploiting massive parallelism, both parallel implementations achieve very high parallel efficiency and nearly linear scalability. The result of this work is that we are able to simulate large-scale nanoelectronic network, within a reasonable time period, which would be impractical on conventional workstations.