A family of network topologies with multiple loops and logarithmic diameter

  • Authors:

  • Srabani Sen Gupta;Rajib K. Das;Krishnendu Mukhopadhyaya;Bhabani P. Sinha

  • Affiliations:

  • Electronics Unit, Indian Statistical Institute, 203, B.T. Road, Calcutta 700 035, India;Electronics Unit, Indian Statistical Institute, 203, B.T. Road, Calcutta 700 035, India;Department of Mathematics, Jadavpur University, Calcutta 700 032, India;Electronics Unit, Indian Statistical Institute, 203, B.T. Road, Calcutta 700 035, India

  • Venue:
  • Parallel Computing
  • Year:
  • 1997

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Abstract

A new family of network topologies containing multiple loops is discussed in this paper. In the proposed structure, N processors are interconnected to form a graph G(m, N), m = 3, where m is a parameter of the graph such that N is an even multiple of m and (m - 1) x 2[(^m^-^ ^l^)^/^2]+