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This paper presents the results of a series of experiments to study the vector performance of the NEC SX-2. The main object of this study is to understand the architecture and identify its bottlenecks and limiting factors. A simple performance model is used to examine the impact of certain architectural features on the performance of a set of basic operations. The results of implementing this set on the machine for four vector lengths and three memory strides are presented and compared. These results show that the vector length and the ratio of floating point operations to memory references have a great impact on the performance of the machine. Two numerical algorithms are also employed and the results of these algorithms and the basic operations are compared to early results on one processor of the Cray-2 and Cray Y-MP. These comparisons show that the SX-2 is faster than the Cray Y-MP by up to 86% for short vectors and by 2 to 4 times for long vectors. Also, it outperformed the Cray-2 by even bigger factors. Finally, the architecture of the SX-X is presented, and some predictions about its performance are given.