Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Structure of Computers and Computations
Structure of Computers and Computations
Control and data dependence for program transformations.
Control and data dependence for program transformations.
Code optimization of pipeline constraints
Code optimization of pipeline constraints
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Phase coupling for horizontal microcode generation
ACM SIGMICRO Newsletter
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A pipelined processor increases its performance by partitioning an instruction into several separate operation steps. Several instructions can be executed in the pipeline in different pipe stages at the same time. Since the overlapped execution of instructions, the result of an instruction may be attempted to be used before it is available.One way to solve this problem is to schedule instructions at compiler time, thus the codes generated will be free from interlocks. The scheduling algorithm presented by [Hen 83, Gro 83] had significantly reduced the pipeline interlocks. With some modifications to distinguish the conflict condition, the algorithm will do better works at the same cost.