CMOS PLL Design in a Digital Chip Environment

  • Authors:

  • Delvan A. Ramey

  • Affiliations:

  • Digital Semiconductor Engineering, Digital Equipment Corporation

  • Venue:
  • Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
  • Year:
  • 1997

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Abstract

CMOS PLL‘s are becoming increasingly useful for clocksynthesis and recovery in CPU and other digital chip designs.However, the packaging and process are defined to meet the requirementsof the digital chip, not the analog portions of the PLL. Theenvironment defined by the digital requirements includes thepackage, the process and the dominant noise source. Packagesfor complex digital chips are larger and have more complex frequencyand signal integrity characteristics than smaller packages thatare appropriate for dedicated analog chips. Digital CMOS processeslack the quality capacitors, resistors and possible variety ofdevices that may be found in a process developed specificallyfor analog purposes. Digital switching causes significant noisethat dominates the spectrum that the circuit designer must worryabout. This paper considers a typical CMOS PLL design from thedigital chip design viewpoint.