Performance of the KORA-2 cache replacement scheme

  • Authors:
  • Humayun Khalid

  • Affiliations:
  • Motorola Inc., PoweerPC Performance, Somerset Design Center, 6200 Bridgepoint Parkway#4, Austin, TX

  • Venue:
  • ACM SIGARCH Computer Architecture News
  • Year:
  • 1997

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Abstract

In this paper, we propose a new strategy (KORA-2) for the replacement of lines in cache memories. The algorithm is efficient and easily implementable. It is basically an extension of our previous work presented in [1]-[5]. Key to our algorithm is to identify and discard inactive lines relatively quickly as opposed to the conventional replacement algorithms. Trace-driven simulations were performed for 42 different cache configurations using benchmark programs from SPEC92 (Standard performance Evaluation Corporation) benchmark suites. Simulation results illustrate that our algorithm can provide a peak value of approximately 8.71% improvement in the miss ratio over the best performing conventional algorithm (LRU) for the selected benchmark trace files generated from SPEC programs. This translates to a savings of hundreds of thousands of misses for typical programs referencing well over 100 million addresses.