Implementation of a high-speed Prolog interpreter

Authors:
A. Krall
Affiliations:
Institut fur Praktische Informatik, Technische Universitt Wien, Argentinerstr.8, A-1040 Wien, Europe
Venue:
SIGPLAN '87 Papers of the Symposium on Interpreters and interpretive techniques
Year:
1987

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Abstract

This paper describes the implementation of a high speed Prolog interpreter on a standard microprocessor (50 KLIPS on a 16 MHz MC68020). The interpreter is based on direct threaded code. By this method an interpreted program achieves the same speed as a compiled program, but uses only a tenth of memory. The first part of this paper describes the implementation of the interpreter. The second part compares the implementation, the runtime and the storage requirements with that of a compiler.