ACM Transactions on Computer Systems (TOCS)
Petri nets: an introduction
Transputer reference manual
Communicating sequential processes
Communications of the ACM
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
International Workshop on Timed Petri Nets
Generalized Stochastic Petri Nets Revisitied: Random Switches and Priorities
PNPM '87 The Proceedings of the Second International Workshop on Petri Nets and Performance Models
Occam Programming Manual
Stochastic Well-Formed Colored Nets and Symmetric Modeling Applications
IEEE Transactions on Computers
Locking Performance in a Shared Nothing Parallel Database Machine
IEEE Transactions on Knowledge and Data Engineering
Generalized Stochastic Petri Nets: A Definition at the Net Level and its Implications
IEEE Transactions on Software Engineering
LISPACK-A Methodology and Tool for the Performance Analysis of Parallel Systems and Algorithms
IEEE Transactions on Software Engineering
A Three-View Model for Performance Engineering of Concurrent Software
IEEE Transactions on Software Engineering
Manual and Automatic Exploitation of Symmetries in SPN Models
ICATPN '98 Proceedings of the 19th International Conference on Application and Theory of Petri Nets
Timed Petri net models of multithreaded multiprocessor architectures
PNPM '97 Proceedings of the 6th International Workshop on Petri Nets and Performance Models
Discovering Architectures from Running Systems
IEEE Transactions on Software Engineering
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A high-level Petri net model of the software architecture of an experimental MIMD multiprocessor system for Artificial Intelligence applications is derived by direct translation of the code corresponding to the assumed workload. Hardware architectural constraints are then easily added, and formal reduction rules are used to simplify the model, which is then further approximated to obtain a performance model of the system based on generalized stochastic Petri nets. From the latter model it is possible to estimate the optimal multiprogramming level of each processor so as to achieve the maximum performance in terms of overall throughput (number of tasks completed per unit time).