Warp architecture and implementation

Authors:
Marco Annaratone;Emmanuel Arnould;Thomas Gross;H. T. Kung;Monica S. Lam;Onat Menzilcioglu;Ken Sarocky;Jon A. Webb
Affiliations:
Department of Computer Science, Carnegie Mellon University, Pittsburg, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburg, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburg, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburg, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburg, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburg, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburg, Pennsylvania;Department of Computer Science, Carnegie Mellon University, Pittsburg, Pennsylvania
Venue:
25 years of the international symposia on Computer architecture (selected papers)
Year:
1998

The architecture of a programmable systolic chip

Advances in VLSI and Computer Systems
Compilation for a high-performance systolic array

SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Memory requirements for balanced computer architectures

ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing

MICRO 14 Proceedings of the 14th annual workshop on Microprogramming

Hi-index	0.00