Estimating the Focus of Expansion in Analog VLSI

Authors:
Ignacio S. McQuirk;Berthold K. P. Horn;Hae-Seung Lee;John L. Wyatt, Jr.
Affiliations:
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139. E-mail: ig@rle-vlsi.mit.edu;Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Cambridge, MA 02139. E-ma bkph@ai.mit.edu;Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139. E-mail: hslee@mtl.mit.edu;Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA 02139. E-mail: wyatt@rle-vlsi.mit.edu
Venue:
International Journal of Computer Vision
Year:
1998

Citing 5
Cited 1

Direct Passive Navigation

IEEE Transactions on Pattern Analysis and Machine Intelligence
Parallel networks for machine vision

Artificial intelligence at MIT
The multiscale veto model: a two-stage analog network for edge detection and image reconstruction

International Journal of Computer Vision
Robot Vision

Robot Vision
An Analog VLSI Chip for Estimating the Focus of Expansion

An Analog VLSI Chip for Estimating the Focus of Expansion

Finding the focus of expansion and estimating range using optical flow images and a matched filter

Machine Vision and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

In the course of designing an integrated system for locating thefocus of expansion (FOE) from a sequence of images taken while a camera istranslating, a variety of direct motion vision algorithms based on imagebrightness gradients have been studied (McQuirk, 1991, 1996b). The locationof the FOE is the intersection of the translation vector of the camera withthe image plane, and hence gives the direction of camera motion. This paperdescribes two approaches that appeared promising for analog very large scaleintegrated (VLSI) circuit implementation. In particular, two algorithmsbased on these approaches are compared with respect to bias, robustness tonoise, and suitability for realization in analog VLSI. From these results,one algorithm was chosen for implementation. This paper also briefly discussthe real-time analog CMOS/CCD VLSI architecture realized in the FOE chip.