VLSI Architecture for Real-Time Edge Linking

Authors:
Amjad Hajjar;Tom Chen
Affiliations:
Colorado State Univ., Fort Collins;Colorado State Univ., Fort Collins
Venue:
IEEE Transactions on Pattern Analysis and Machine Intelligence
Year:
1999

Citing 4
Cited 4

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Abstract

A real-time algorithm and its VLSI implementation for edge linking is presented in this paper. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n + 12 clock cycles, where n is the number of pixel columns in the image.