Performance prediction tools for parallel discrete-event simulation

  • Authors:
  • Chu-Cheow Lim;Yoke-Hean Low;Boon-Ping Gan;Sanjay Jain;Wentong Cai;Wen Jing Hsu;Shell Ying Huang

  • Affiliations:
  • Gintic Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore;Gintic Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore;Gintic Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore;Gintic Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore;Centre for Advanced Information Systems, School of Applied Science, Nanyang Technological University, Singapore 639798, Singapore;Centre for Advanced Information Systems, School of Applied Science, Nanyang Technological University, Singapore 639798, Singapore;Centre for Advanced Information Systems, School of Applied Science, Nanyang Technological University, Singapore 639798, Singapore

  • Venue:
  • PADS '99 Proceedings of the thirteenth workshop on Parallel and distributed simulation
  • Year:
  • 1999

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Abstract

We have developed a set of performance prediction tools which help to estimate the achievable speedups from parallelizing a sequential simulation. The tools focus on two important factors in the actual speedup of a parallel simulation program : (a) the simulation protocol used, and (b) the inherent parallelism in the simulation model. The first two tools are a performance/parallelism analyzer for a conservative, asynchronous simulation protocol, and a similar analyzer for a conservative, synchronous ("super-step") protocol. Each analyzer allows us to study how the speedup of a model changes with increasing number of processors, when a specific protocol is used. The third tool -- a critical path analyzer -- gives an ideal upper bound to the model's speedup. This paper gives an overview of the prediction tools, and reports the predictions from applying the tools to a discrete-event wafer fabrication simulation model. The predictions are close to speedups from actual parallel implementations. These tools help us to set realistic expectations of the speedup from a parallel simulation program, and to focus our work on issues which are more likely to yield performance improvement.