On the Time-Bandwidth Proof in VLSI Complexity

Authors:
Y. S. Abu-Mostafa
Affiliations:
-
Venue:
IEEE Transactions on Computers
Year:
1987

Citing 3
Cited 0

Information Theory and Reliable Communication

Information Theory and Reliable Communication
A complexity theory for VLSI

A complexity theory for VLSI
Computational Aspects of VLSI

Computational Aspects of VLSI

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Abstract

A subtle fallacy in the original proof [1] that the computation time T is lowerbounded by a factor inversely proportional to the minimum bisection width of a VLSI chip is pointed out. A corrected version of the proof using the idea of conditionally self-delimiting messages is given.