Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Fault-Tolerant Computing
Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test Experiments
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A New Analog Parametric Self-Disconnecting BIC Sensor Class
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
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We present a high qualitative reconfigurability method forfault-tolerant memory systems against radiation influence onsemiconductors. Its novelty lies in a joint failure repairmechanism. It uses a concurrent on-line technique based on asynchronous built-in current sensors (BICS), parity check and cold spare modules against electrical abnormal behaviour due tolatch-up (LU), and the Hamming SEC code to counterattack singleerror upset (SEU), manifested in logical failures. Completereliability computations, which underlie the proposed scheme, searchfor a 99.902% tolerance, thought to meet typical spatial irradiationconditions, to the cost of a small hardware overhead (2 spare(additional) 1K1 modules for each 1K16 of a memory system of 512K16,and Mean Time To Failure = 10−7 h−1). Finally, as weenvisage a 2.4 μm CMOS implementation, we performed complexityestimations, which show that the supplementary self-toleranceensuring circuitry involves an overhead of 0.0094% for a 512K16memory. The recovering latency is minimised. For SEU in DRAM itrequires zero latency and no more than the duration of an equivalentrefresh cycle in SRAM. LU reflects a locality property, as only theaffected module is submitted to the recovering algorithm.