Compact High Gain CMOS Op Amp Design using Comparators

Authors:
Hoda S. Abdel-Aty-Zohdy;John Purcell
Affiliations:
Microelectronics System Design Lab, Director, Electrical and Systems Engineering, Oakland University, Rochester MI, 48309-4401 zohdyhsa@oakland.edu;Microelectronics System Design Lab, Director, Electrical and Systems Engineering, Oakland University, Rochester MI, 48309-4401
Venue:
Analog Integrated Circuits and Signal Processing - Special issue: papers from the 40th midwest symposium
Year:
1999

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Abstract

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 μm nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 μm×474 μm.