Journal of the ACM (JACM)
Data Structures and Algorithms
Data Structures and Algorithms
PLAY: pattern-based symbolic cell layout: Part I: transistor placement
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
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A graph model is proposed to capture the topological properties of metal-oxide semiconductor (MOS) transistors and interconnections among transistors. A set of algorithms is devised for the enumeration of layout topologies of a circuit from its graph model. Layout topologies are presented in stick diagrams. The algorithms select a set of embedded layout topologies with the “fewest” number of jumpers for layout generation and compaction. Layouts for circuits with up to 36 transistors have been generated successfully. The layouts corresponding to the topologies generated and selected by the algorithms are, in most cases, smaller than compact hand layouts. The worst case computational complexity is O(n 2), where n is the number of transistors in the circuit.