The Silc silicon compiler: language and features
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Zeus: A hardware description language for VLSI
DAC '83 Proceedings of the 20th Design Automation Conference
Computer aided design (CAD) using logic programming
DAC '84 Proceedings of the 21st Design Automation Conference
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This paper discusses design for testability automation within a silicon compiler environment under development at GTE Laboratories Inc. The proposed rule-based modular design for testability methodology utilizes both BIST and scan path techniques for full custom VLSI designs. An on-chip test controller may be used. Testability evaluation is performed using both controllability/observability and information theoretic methods. A testability “expert” is required which can manage the analysis as it evolves during the synthesis process and which can make the ultimate testability decisions. Problems involved with integrating the approach with an emerging silicon compilation system are discussed.