A frame-based approach to hardware verification (abstract only)

• Authors: Wei Si Jiang;William G. Wee
• Venue: CSC '87 Proceedings of the 15th annual conference on Computer Science
• Year: 1987

There are currently several approaches to deciding whether or not the hardware design meets its functional specifications[1]. The most frequently-used approach is to design and build the system (or a simulation of it) and try it out on test cases. Except for the simplest systems, it is almost impossible to try a system on all possible cases. Hence this approach cannot guarantee that the design is correct. An alternate approach is to design the system and prove formally that it meets its functional specifications. Theoretically this approach is more powerful than the former though it has some implementation problems. Our approach belongs to this category.Given the behavior of the components of a system and their interconnections, it is possible for a computer program to derive a description of the behavior of the whole system [3, 4], which can be then compared with the design specifications. This is the key point of our approach to hardware verification.Knowledge representation is one of the most important aspects of a reasoning system. In our program, we use frames to represent functional units. Each frame represents a finite state machine (the number of state variables can be zero), which corresponds to a hardware component. For example, we can express a register in the following way: reg isa((value : primitive)) input((value : In)) output((value : Out)) state((value : S),(next : S1)) equal((Out, S), (S1, In)) where equal is a special kind of slot. Using the built-in preprocessor, the system will translate the register frame into the following Prolog clauses: reg(isa, value, primitive). reg(input, value, In). reg(output, value, Out). reg(state, value, S). reg(state, next, S1). reg(equal, reg(output, value, X), reg(state, value, X)). reg(equal,reg(state, next, X), reg(input, value, X)).Each frame has isa and hasparts slots (a primitive frame does not have a hasparts slot) for communications with its parent and children frames. In this way, a hierarchical structure can be built and exploited easily and efficiently, which has proven to be very important for hardware verification [1]. This frame-based approach is one of the important differences between previously published work and ours.Our system was built using our expert system shell PAIS-I which is written in Prolog and C and supports frame-based knowledge representation. The program consists of five major parts: frame manipulation facilities, inference engine, interface, a subsystem for simplifying symbolic expressions, and knowledge base. The interface is capable of handling a direct access to a relational database [2]. This capability facilitates keeping a large number of frames representing those frequently-used hardware units in the secondary storage and makes efficient retrieval easier as well. This is another important feature of our system.Our program is also capable of handling the timing aspect in the hardware design (each finite state machine unit can have four phases). Several functional units of simple or medium complexity, such as counters and full adders, were verified successfully. A simplified Intel 8085 microprocessor was also tested, and the results were encouraging. We are going to test Intel 8085 in more detail. We also plan to improve the explanation facilities, which are not satisfactory at the moment.