Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications

  • Authors:
  • Mladen Berekovic;Helge Kloos;Peter Pirsch

  • Affiliations:
  • Laboratorium für Informationstechnologie, Universität Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Germany

  • Venue:
  • Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation
  • Year:
  • 1999

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Abstract

This paper describes a new architecture for JAVA-based,interactive multimedia applications. A hardware implementation of aJava Virtual Machine (JVM) is proposed, which allows the directexecution of Java bytecode. In a single clock cycle, up to 3 bytecodeinstructions can be decoded and executed in parallel using a RISCpipeline. A splitable 64-bit ALU implementation addresses demandingprocessing requirements of typical multimedia signal processingschemes. The on-chip caches are adapted to the specific datastructures of the JVM. The proposed architecture supports executionof multiple Java threads in parallel. An implementation ofbasic building blocks of the processor with a standard-celllibrary provides an estimate of 150 MHz clock-speed for a 0.35 μm3 metal layer CMOS process. With a size of less than 10 mm^2 neededfor the core logic, it is possible to integrate multiple JVMstogether with larger cache memories on a single chip. Based on theseresults, we discuss various performance aspects of JAVA for use infuture multimedia terminals.