ACM Transactions on Programming Languages and Systems (TOPLAS)
Information and Computation - Semantics of Data Types
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Veritas+: a specification language based on type theory
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
Fundamentals of Deductive Program Synthesis
IEEE Transactions on Software Engineering
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Journal of the ACM (JACM)
Implementation of the Veritas Design Logic
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
Generic System Support for Deductive Program Development
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Formal design of a class of computers
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Logic Frameworks for Logic Programs
LOPSTR '94/META '94 Proceedings of the 4th International Workshops on Logic Programming Synthesis and Transformation - Meta-Programming in Logic
Hardware Verification using Monadic Second-Order Logic
Proceedings of the 7th International Conference on Computer Aided Verification
Designing Arithmetic Circuits by Refinement in Ruby
Proceedings of the Second International Conference on Mathematics of Program Construction
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Formal Synthesis is a methodology developed at the university of Kentfor combining circuit design and verification, where a circuit isconstructed from a proof that it meets a given formal specification.We have reinterpreted this methodology in ISABELLE‘S theory ofhigher-order logic so that circuits are incrementally built duringproofs using higher-order resolution. Our interpretation simplifiesand extends Formal Synthesis both conceptually and in implementation.It also supports integration of this development style with otherproof-based synthesis methodologies and leads to techniques fordeveloping new classes of circuits, e.g., recursive descriptions ofparametric designs.