IEEE Transactions on Circuits and Systems for Video Technology
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A new emulated digital CNN Universal Machine chiparchitecture is introduced and the main steps of the design processare shown in this paper. One core processor can be implemented on2 × 2 mm^2 silicon area with a 0.35 μm CMOStechnology. Assuming an array of 24 processors on a chip, its speedis 1ns/virtual cell/CNN iteration with 12 bit precision. This enablesthe execution of over five hundred 3 × 3 convolutionoperations on each frame of a 240 × 320-pixel 25 fpsdigital image flow. Another new feature of the designis its variable precision capability. This allows the user to tradeoff precision for speed. The architecture supports some non-linearfilter implementation as well.