Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Pipelined processors and worst case execution times
Real-Time Systems
Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Coloured Petri nets (2nd ed.): basic concepts, analysis methods and practical use: volume 1
Coloured Petri nets (2nd ed.): basic concepts, analysis methods and practical use: volume 1
Pipeline behavior prediction for superscalar processors by abstract interpretation
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Design/CPN - A Computer Tool for Coloured Petri Nets
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
A Worst Case Timing Analysis Technique for Multiple-Issue Machines
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
A visualization-based microarchitecture workbench
A visualization-based microarchitecture workbench
Real-Time Performance Estimation for Dynamic, Distributed Real-Time Systems
ICCS '02 Proceedings of the International Conference on Computational Science-Part III
Important Considerations for Execution time Analysis of Dynamic, Periodic Processes
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Adaptive resource management for dynamic distributed real-time applications
The Journal of Supercomputing
An accurate and efficient simulation-based analysis for worst case interruption delay
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
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Determining a tight WCET of a blockof code to be executed on a modern superscalar processor architectureis becoming ever more difficult due to the dynamic behaviourexhibited by current processors, which include dynamic schedulingfeatures such as speculative and out-of-order execution in thecontext of multiple execution units with deep pipelines. We describethe use of Coloured Petri Nets (CP-nets) in a simulation basedapproach to this problem. A complex model of a generic processorarchitecture is described, with emphasis on the modelling strategyfor obtaining the WCET and an analysis of the results.