Equivalence checking of arithmetic expressions using fast evaluation
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Expression equivalence checking using interval analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we introduce presynthesis optimizations on hardware description languages (HDLs). Presynthesis optimizations consist of two categories of tasks: 1) source-level transformations, which produce optimized behavioral HDL descriptions that lead to improved synthesis results and 2) source-level analysis, which produces information useful in the synthesis stage to improve the quality of the synthesized circuits. Presynthesis optimizations are carried out on an intermediate tabular representation called timed decision table (TDT). We have implemented the TDT-based presynthesis optimization algorithms in a software package called Pumpkin. Experiments running Pumpkin on named benchmarks show promising results.