A Smart-Scanning Analog VLSI Visual-Attention System

  • Authors:
  • Tonia G. Morris;Stephen P. De Weerth

  • Affiliations:
  • School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250 U.S.A.;School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250 U.S.A.

  • Venue:
  • Analog Integrated Circuits and Signal Processing - Special issue on selected papers from ECS '97
  • Year:
  • 1999

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Abstract

We have implemented a hardware model of selective visual attention within the neuromorphic, analog VLSI paradigm. The system includes a highly-parallel winner-take-all selection with excitatory and inhibitory influences. The selection specifies positions of attention based on an array of intensity levels, which comprise a primitive saliency map. The excitation and inhibition control the strategy for shifts of attention from one position to the next. The combination of these fundamental building blocks demonstrates emergent properties that can be observed in real time due to the parallel hardware implementation. The system behaves as a smart-scanning sensor array. The basic characteristics of the scanning pattern are controlled by setting a number of analog parameters. In this paper we describe the system, focusing on the role that inhibition plays in the redirection of attention. We show experimental results from one-dimensional implementations of the hardware model. Analysis that explains the expected behavior for the two-element mode of operation is presented. The theoretical predictions are compared to experimental results.