Statistical Design of Low Power Square-Law CMOS Cells for High Yield

Authors:
Tuna B. Tarim;H. Hakan Kuntman;Mohammed Ismail
Affiliations:
Currently with Texas Instruments, Dallas, TX. Previously a visiting scholar with the Analog VLSI Lab The Ohio State University, Columbus, Ohio, USA;Department of Electronics Engineering, Istanbul Technical University, Istanbul, Turkey kuntman@ehb.itu.edu.tr;The Analog VLSI Lab, Department of Electrical Engineering, Ohio State University, Columbus, Ohio, USA ismail@ee.eng.ohio-state.edu
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2000

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Abstract

A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.