Two algorithms for barrier synchronization
International Journal of Parallel Programming
A bridging model for parallel computation
Communications of the ACM
High speed synchronization of processors using fuzzy barriers
International Journal of Parallel Programming
Efficient techniques for fast nested barrier synchronization
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
The simultaneous optical multiprocessor exchange bus
MPPOI '95 Proceedings of the Second Workshop on Massively Parallel Processing Using Optical Interconnections
Tiered Algorithm for Distributed Process Quiescence and Termination Detection
IEEE Transactions on Parallel and Distributed Systems
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Barrier synchronization is a useful parallel programming construct for ensuring that all processors are at a particular location in the code before any processor is allowed to continue. Barrier synchronization is integral to programming models such as the Bulk Synchronous Parallel model. Specialized hardware is often used to improve the performance of a barrier synchronization operation. With continued improvement in processor performance, more efficient synchronization mechanisms are required to counter the rising relative cost of synchronization operations. A high-speed, distributed barrier synchronization mechanism has been developed for broadcast-based optical interconnection networks. This mechanism avoids multiple conversions between optical and electrical signals by having each processor locally decide whether the barrier in which it is participating has been satisfied. It also allows arbitrary sized partitions to be built dynamically during the execution of a program. Simulations of the current hardware design estimate that the barrier synchronization requires less than 300ns for a 128-processor system.