Highly regular, modular, and cascadable design of cellular automata-based pattern classifier

Authors:
Santanu Chattopadhyay;Shelly Adhikari;Sabyasachi Sengupta;Mahua Pal
Affiliations:
Indian Institute of Technology, Guwahati, India;Delsoft India Pvt., Ltd., Noida, India;Wipro Technologies, Bangalore, India;WIPRO Infotech, Calcutta, India
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Year:
2000

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Abstract

This paper enumerates a new approach to the solution of classification problems based on the properties of Additive Cellular Automata. Classification problem plays a major role in various fields of computer science, such as grouping of the records in database systems, detection of faults in VLSI circuits, image processing, and so on. The state-transition graph of Non-group Cellular Automata (CA) consists of a set of disjoint trees rooted at some cyclic states of unit cycle length - thus forming a natural classifier. First a scheme of classifying the patterns distributed into only two classes has been dealt with. This has been further extended for solution of the multiclass classification problem. The Multiclass Classifier saves on an average 34% of memory as compared to the straight-forward approach storing directly the class of each pattern. A regular, modular, and cascadable hardware implementation of the classifier has been presented which is highly suitable for VLSI realization. The design has been specified in Verilog and verified for functional correctness.