Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits

  • Authors:

  • Bassam Shaer;David Landis;Sami A. Al-Arian

  • Affiliations:

  • Univ. of Minnesota, Duluth;Pennsylvania State Univ., University Park;Univ. of South Florida, Tampa

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
  • Year:
  • 2000

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Abstract

This brief introduces a partitioning algorithm, which facilitates pseudoexhaustive testing, to detect and locate faults in digital VLSI circuits. The algorithm is based on an analysis of circuit's primary input cones and fanout (PIFAN) values. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous ISCAS 1985 and 1989 benchmark circuits containing up to 5597 gates. Our results show that the PIFAN algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms.