ATM traffic shaper: ATS

Authors:
J. C. Diaz;P. Plaza;J. Crespo
Affiliations:
Telefónica Investigación y Desarrollo, Madrid (SPAIN);Telefónica Investigación y Desarrollo, Madrid (SPAIN);Telefónica Investigación y Desarrollo, Madrid (SPAIN)
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

Citing 2
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Simulation Modeling and Analysis

Simulation Modeling and Analysis
Design and validation with HDL Verilog of a complex input/output processor for an ATM switch: the CMC

IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference

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Abstract

The design and Implementation of an ATM Traffic Shaper (ATS) is here described. This IC was realized on a 0.35m CMOS technology. The main function of the ATS is the collection of low bit rate traffics to fill a higher bit rate pipe in order to reduce the cost of ATM based services, nowadays mainly influenced by transmission cost. The circuit fits in several ATM system configurations but mainly will be used at the User-Network Interfaces or Network-Network interfaces. The IC was designed with a Top-Down methodology using as HDL, Verilog. The Chip is pad limited and is encapsulated on a 208 PQFP Package. The circuit complexity is 38 Kgates and its working frequency is 32Mhz. A circuit prototype was build with FPGAs in order to validate the RTL description.