Automating the sizing of analog CMOS circuits by consideration of structural constraints
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hierarchical constraint transformation using directed interval search for analog system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Hierarchical constraint transformation based on genetic optimization for analog system synthesis
Integration, the VLSI Journal
Hierarchical constraint transformation based on genetic optimization for analog system synthesis
Integration, the VLSI Journal
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This paper presents a new method for hierarchical characterization of analog integrated circuits. For each circuit class, a fundamental set of performances is defined and extracted topology independently. A circuit being characterized is decomposed in general subcircuits. Sizing rules of these topology independent subcircuits are included into the characterization by functional constraints. In this way, bad circuit sizing is detected and located.