Realtime wavelet video coder based on reduced memory accessing

Authors:
Roberto Y. Omaki;Yu Dong;Morgan H. Miki;Makoto Furuie;Daisuke Taki;Masaya Tarui;Gen Fujita;Takao Onoye;Isao Shirakawa
Affiliations:
Dept. Information Sys Eng., Osaka University Suita, Osaka 565-0871;Dept. Information Sys Eng., Osaka University Suita, Osaka 565-0871;Dept. Information Sys Eng., Osaka University Suita, Osaka 565-0871;Dept. Information Sys Eng., Osaka University Suita, Osaka 565-0871;Dept. Information Sys Eng., Osaka University Suita, Osaka 565-0871;Dept. Information Sys Eng., Osaka University Suita, Osaka 565-0871;Dept. Information Sys Eng., Osaka University Suita, Osaka 565-0871;Dept. Comm. & Computer Eng., Kyoto University, Kyoto, Kyoto 606-8501;Dept. Information Sys Eng., Osaka University Suita, Osaka 565-0871
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

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Abstract

In this paper, the VLSI implementation of a real-time EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93 x 4.93 mm2 die.