A real-time 64-monosyllable recognition LSI with learning mechanism

  • Authors:

  • Kazuhiro Nakamura;Qiang Zhu;Shinji Maruoka;Takashi Horiyama;Shinji Kimura;Katsumasa Watanabe

  • Affiliations:

  • Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101 Japan;Fujitsu Laboratories Ltd and Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101 Japan;Hitachi Ltd and Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101 Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101 Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101 Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101 Japan

  • Venue:
  • Proceedings of the 2001 Asia and South Pacific Design Automation Conference
  • Year:
  • 2001

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Abstract

In the paper, a real-time 64-mono-syllable recognition LSI is presented. The LSI accepts 11.6 msec speech frame and outputs a 6-bit symbol-code for each frame by the end of the next frame with the pipelining manner. The recognition method is based on the Hidden Markov Model and is speaker-independent. An on-chip learning mechanism has also been designed, but the circuit is off-chip at present implementation because of the restriction of LSI area. The LSI is fabricated by VDEC Rohm with 0.6 um process on a 4.5 mm x 4.5 mm chip.