Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
A novel framework of register allocation for software pipelining
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis
VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis
A Polynomial Time Method for Optimal Software Pipelining
CONPAR '92/ VAPP V Proceedings of the Second Joint International Conference on Vector and Parallel Processing: Parallel Processing
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In this paper, we address the problem of minimizing buffer storage requirement in buffer binding for SDF (Synchronous Dataflow) graphs. First, we propose a new two-port FIFO buffer structure that can be efficiently shared by two producer/consumer pairs. Then we propose a buffer binding algorithm based on this two-port buffer structure for minimizing the buffer size requirement. Experimental results demonstrate 9.8%~37.8% improvement in buffer requirement compared to the conventional approaches.