The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machines

  • Authors:

  • Andrew A. Duncan;David C. Hendry;Peter Gray

  • Affiliations:

  • Univ. of Aberdeen, Kings College, Aberdee, U. K.;Univ. of Aberdeen, Kings College, Aberdee, U. K.;Univ. of Aberdeen, Kings College, Aberdee, U. K.

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
  • Year:
  • 2001

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Abstract

This paper describes the column oriented butted regular architecture-algorithmic behavioral synthesis (COBRA-ABS) high-level synthesis tool which has been designed to synthesize DSP algorithms, specified in C, onto multi-field programmable gate array (FPGA) custom computing machines (FCCMs). COBRA-ABS performs synthesis using a new simulated annealing-based methodology, which maps the specified behavior into a four-dimensional (4-D) space and then optimizes the implied architecture. COBRA-ABS synthesizes custom very long instruction word (VLIW) style architectures partitioned across the FPGAs of the FCCM and has been used to compile C algorithms down to FPGA configuration bit-streams. This paper describes the tool and synthesis concepts and presents simulation results from a number of synthesized fast Fourier transform (FFT) related algorithms.