Predicting potential COBOL performance on low level machine architectures

• Authors: Jerome A. Otto
• Venue: ACM SIGPLAN Notices
• Year: 1985

As a COBOL host, a computer architecture should efficiently execute those language constructs that are most frequently used in actual programs. However, when the language's control and data structures are at a far higher level than the control and data structures of the underlying machine, the compiler designer is faced with a large number of potential choices for mapping these high level structures to the low level architecture. This is the case for implementing COBOL on a typical mini-computer architecture. Restricting the choices to an implementable set meeting a given performance criteria and predicting the resulting performance level requires a complex analysis. This paper gives an example of the methodology used in one such analysis -- the performance of COBOL on low level architectures. This area was chosen because of the difficulty of the problem caused by the lack of support for COBOL constructs and data types on low level architectures used in most mini-and micro-computers. The Motorola MC68000 and a RISC-type architecture were selected as representative architectures.