Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design

Authors:
Hung-Pin Wen;Chien-Yu Lin;Youn-Long Lin
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Venue:
Proceedings of the 14th international symposium on Systems synthesis
Year:
2001

Citing 8
Cited 0

Internetworking with TCP/IP vol III (2nd ed.): client-server programming and applications BSD socket version

Internetworking with TCP/IP vol III (2nd ed.): client-server programming and applications BSD socket version
WELD—an environment for Web-based electronic design

DAC '98 Proceedings of the 35th annual Design Automation Conference
Specification and validation of disstributed IP-based designs with JavaCAD

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Virtual simulation of distributed IP-based designs

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Web-CAD methodology for IP-core analysis and simulation

Proceedings of the 37th Annual Design Automation Conference
Principles of VERILOG PLI

Principles of VERILOG PLI
The VERILOG PLI Handbook: A User's Guide and Comprehensive Reference on the VERILOG Programming Language Interface

The VERILOG PLI Handbook: A User's Guide and Comprehensive Reference on the VERILOG Programming Language Interface
Distributed EDA Tool Integration: The PPP Paradigm

ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose an Internet-based concurrent-simulation scheme to ease IP evaluation process between IP vendors and users. Complex system-on-a-chip design requires more and more IP modules from 3rd party vendors. What can be disclosed by the vendor without impairing its trade secrete and what needs to be examined by the user to gain satisfactory level of confidence are contradictory of each other. Via PLI interface functions and Internet protocol, our proposed software enables HDL simulators (Verilog) residing in both the vendor and user's sites to concurrently simulate the IP and SOC together. Only stimulus and response defined in the IP's I/O are exchanged between the sites. Therefore, the vendor need not to create a functional model (or encrypted code) for the IP while the user is assured what he/she simulates is what he will purchase. Beside simulation speed degradation due to communication overhead, the SOC design/debug process is exactly same as if the IP is in the user's hand. Our contribution will help all IP providers expose their IPs to all potential users without human intervention and IP right infringement concern.