False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Authors:
Jing-Jia Liou;Angela Krstic;Li-C. Wang;Kwang-Ting Cheng
Affiliations:
University of California, Santa Barbara, CA;University of California, Santa Barbara, CA;University of California, Santa Barbara, CA;University of California, Santa Barbara, CA
Venue:
Proceedings of the 39th annual Design Automation Conference
Year:
2002

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Abstract

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.