Journal of the ACM (JACM)
Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Interconnection networks and compiler algorithms for multiprocessors
Interconnection networks and compiler algorithms for multiprocessors
On the Rearrangeability of 2(Iog2N) -1 Stage Permutation Networks
IEEE Transactions on Computers
A Self-Routing Benes Network and Parallel Permutation Algorithms
IEEE Transactions on Computers
The Reverse-Exchange Interconnection Network
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
On a Class of Rearrangeable Networks
IEEE Transactions on Computers
A Fast Parallel Algorithm for Routing Unicast Assignments in Benes Networks
IEEE Transactions on Parallel and Distributed Systems
Fault Diagnosis in a Benes Interconnection Network
IEEE Transactions on Parallel and Distributed Systems
IEEE/ACM Transactions on Networking (TON)
Work-Efficient Routing Algorithms for Rearrangeable Symmetrical Networks
IEEE Transactions on Parallel and Distributed Systems
A new approach to fast control of r2× r2 3-stage benes networks of r×r crossbar switches
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
On Evil Twin Networks and the Value of Limited Randomized Routing
IEEE Transactions on Parallel and Distributed Systems
Performing Permutations on Interconnection Networks by Regularly Changing Switch States
IEEE Transactions on Parallel and Distributed Systems
Performance analysis and fault tolerance of randomized routing on Clos networks
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
A General Inside-Out Routing Algorithm for a Class of Rearrangeable Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
| Hi-index | 14.98 |
A new Benes network control algorithm is presented. Unlike the original looping algorithm, the new algorithm is not recursive. In this algorithm (N x N) Benes network is viewed as a concatenation of two subnetworks SN1 and SN2. The first (log N - 1) stages of a Benes network correspond to SN1, and the remaining log N stages correspond to SN2. SN1 is controlled by a full binary tree of set partitioning functions, called a Complete Residue Partition Tree, and SN2 is bit controlled. The new control algorithm sets switches one stage at a time, stage by stage.