ACM Transactions on Programming Languages and Systems (TOPLAS)
ACM Computing Surveys (CSUR) - The MIT Press scientific computation series
Computer
Stencils and problem partitionings: their influence on the performance of multiple processor systems
IEEE Transactions on Computers
Experimental analysis of layered Ethernet software
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
ACM Transactions on Computer Systems (TOCS)
Implementing remote procedure calls
ACM Transactions on Computer Systems (TOCS)
The distributed V kernel and its performance for diskless workstations
SOSP '83 Proceedings of the ninth ACM symposium on Operating systems principles
An introduction to network computers
ACM '82 Proceedings of the ACM '82 conference
Demand Assignment Multiple Access Schemes in Broadcast Bus Local Area Networks
IEEE Transactions on Computers
Implementing Fault-Tolerant Distributed Objects
IEEE Transactions on Software Engineering
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A bus network design is provided that improves communications between operational CPU's by 1-2 orders of magnitude over present distributed system LANs. Bus networking is chosen over point-to-point coupling (cube connected architectures) because 1) reconfiguration for different tasks is not necessary, 2) the system can support heterogeneous nodes and mulitlevel parallelism, and 3) its physical structure supports reliability and evolution more readily.The design provides multiple messages per access by framed virtual circuitry in order to minimize delays and provides backplane-to-backplane data protocols transfers. When software protocol handling is eliminated, communications speeds increase significantly. It also supports local read-“global” write paradigm to effect a shared memory machine. However, extremely flexible buffering scheme allows each node to operate autonomously in both time and data handling. Thus, multilevel, potentially heterogeneous parallelism is available for implementation at the kernel and operating system level. The paper describes the integrated network and node communications interface design and presents expected performance figures.