Cache memory optimization to reduce processor/memory traffic
Advances in VLSI and Computer Systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Real-Time Synchronization of Interprocess Communications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Finding an extremum in a network
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Dynamic decentralized cache schemes for mimd parallel processors
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Coordinating parallel processors: a partial unification
ACM SIGARCH Computer Architecture News
Software structures for ultraparallel computing
Software structures for ultraparallel computing
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The problem of computing the maximum of n inputs on an asynchronous parallel computer is considered. In general, the inputs may arrive staggered in time, the number of processors available to the maximization algorithm may vary during its execution, and the number of inputs, n, may be initially unknown. Two simple, efficient algorithms to compute the maximum are presented. Each algorithm may be invoked asynchronously, as new inputs and processors arrive. Performance measures that account for the response times of the invocations are introduced, and the algorithms are analyzed under these measures.