Simulation Modeling and Analysis
Simulation Modeling and Analysis
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In this paper, a scheduling heuristic was developed to aid the operators in semiconductor fabs in choosing what type of lots to process next on bottleneck facilities and whether to change machine setup in order to reduce cycle time. The scheduling heuristic aims at balancing workload levels for implanters processing lots at different stages of the wafer production lifecycle. This is accomplished by processing lots that contribute most to increasing inventory levels at the bottleneck facility. A whole production line simulation model was used to evaluate the performance of the scheduling heuristic and to compare it against several commonly used scheduling heuristics with respect to mean cycle time, work in process (WIP), and standard deviation of cycle time. Simulation results showed that the heuristic performed better than all other rules in terms of mean cycle time and WIP in all cases, and better in terms of standard deviation of cycle time for most cases tested.