Design techniques for low power high bandwidth upconversion in CMOS

Authors:
Carl De Ranter;Michiel Steyaert
Affiliations:
Katholieke Universiteit Leuven, Leuven, Belgium;Katholieke Universiteit Leuven, Leuven, Belgium
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

Citing 3
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Abstract

An upconvertor topology for low power, high bandwidth applications is presented. Using specific circuit techniques and local circuit-level optimization, the power consumption of the total system comprising an on-chip LC-type VCO, a polyphase network quadrature generator, a linear mixer block and an RF-current buffer, has been minimized.A chip has been designed and manufactured in a 0.25&mgr;m CMOS technology. The VCO oscillates between 1.68 GHz and 2 GHz. Driven by an external LO, the transmitter operates from 900 MHz up to 2 GHz. At 2 GHz, the upconvertor transmits -12 dBm into 50 ω with a linearity of more than -35 dBc for base band signals up to 33 MHz.