Communications of the ACM
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Insulin: An Instruction Set Simulation Environment
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
| Hi-index | 0.00 |
This paper presents a technique for simulating processors and attached hardware using the principle of compiled simulation. Unlike existing, in-house and off-the-shelf hardware/software co-simulators, which use interpretive processor simulation, the proposed technique performs instruction decoding and simulation scheduling at compile time. The technique offers up to three orders of magnitude faster simulation. The high speed allows the user to explore algorithms and hardware/software trade-offs before any hardware implementation. In this paper, the sources of the speedup and limitations of the technique are analyzed and the realization of the simulation compiler is presented.