An artificial neural network integrated circuit base on MNOS/CCD principles
AIP Conference Proceedings 151 on Neural Networks for Computing
VLSI architectures for implementation of neural networks
AIP Conference Proceedings 151 on Neural Networks for Computing
Scientific American
On the Problem of Local Minima in Backpropagation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Neural network approach to zero-one optimal covering problem
ANSS '91 Proceedings of the 24th annual symposium on Simulation
VLSI Architectures for Neural Networks
IEEE Micro
Challenges of massive parallelism
IJCAI'93 Proceedings of the 13th international joint conference on Artifical intelligence - Volume 1
Paper: An application of neural networks on channel routing problem
Parallel Computing
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The authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model. It consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The circuit can be operated in several different configurations by programming the interconnections between the processors. Tests made with the circuit working as an associative memory and as a pattern classifier were so encouraging that the chip has been interfaced to a minicomputer and is being used as a coprocessor in pattern-recognition experiments. This mode of operation is making it possible to test the chip's behavior in a real application and study how pattern-recognition algorithms can be mapped in such a network.