A Complementary Pair of Four-Terminal Silicon Synapses

  • Authors:

  • Chris Diorio;Paul Hasler;Bradley A. Minch;Carver Mead

  • Affiliations:

  • Physics of Computation Laboratory, California Institute of Technology, Pasadena, CA 91125, USA;Physics of Computation Laboratory, California Institute of Technology, Pasadena, CA 91125, USA;Physics of Computation Laboratory, California Institute of Technology, Pasadena, CA 91125, USA;Physics of Computation Laboratory, California Institute of Technology, Pasadena, CA 91125, USA

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 1997

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Abstract

We have developed a complementary pair of pFETand nFET floating-gate silicon MOS transistors foranalog learning applications. The memory storage is nonvolatile;hot-electron injection and electron tunneling permit bidirectionalmemory updates. Because these updates depend on both the storedmemory value and the transistor terminal voltages, the synapsescan implement a learning function. We have derived a memory-updaterule for both devices, and have shown that the synapse learningfollows a simple power law. Unlike conventional EEPROMs, thesynapses allow simultaneous memory reading and writing. Synapsetransistor arrays can therefore compute both the array output,and local memory updates, in parallel. We have fabricated prototypesynaptic arrays; because the tunneling and injection processesare exponential in the transistor terminal voltages, the writeand erase isolation between array synapses is better than 0.01 percentThe synapses are small, and typically are operated at subthresholdcurrent levels; they will permit the development of dense, low-powersilicon learning systems.