A set of combinators for abstraction in linear space
Information Processing Letters
Toward the design of a parallel graph reduction machine: the MARS project
Proc. of a workshop on Graph reduction
Specification of reduction strategies in term rewriting systems
Proc. of a workshop on Graph reduction
Evaluating functional programs on the FLAGSHIP machine
Proc. of a conference on Functional programming languages and computer architecture
GRIP—A high-performance architecture for parallel graph reduction
Proc. of a conference on Functional programming languages and computer architecture
Mechanisms for efficient multiprocessor combinator reduction
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
Linear logic and permutation stacks—the Forth shall be first
ACM SIGARCH Computer Architecture News - Special issue: panel sessions of the 1991 workshop on multithreaded computers
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We describe the MaRS machine: a parallel, distributed control multiprocessor for graph reduction using a functional machine language. The object code language is based on an optimized set of combinators, and its functional character allows an automatic parallelisation of the execution. A programming language, "MaRS LISP", has also been developed. A prototype of MaRS is currently being designed in VLSI 1.5-micron CMOS technology with 2 levels of metal, by means of a CAD system. The machine uses three basic types of processors for Reduction, Memory and Communication, plus auxiliary I/O and Arithmetic Processors; communications do not constitute an operational bottleneck, as interprocessor messages are routed via an Omega switching network. Initially, a Host Computer will be used for startup, testing and direct memory access. The machine architecture and its functional organization are described, as well as the theoretical execution model. We conclude on a number of specialized hardware and software mechanism that differentiate MaRS machine from other similar projects currently going on.