A Formal Model for SDL Specifications Based on Timed Rewriting Logic

  • Authors:

  • L. J. Steggles;P. Kosiuczenko

  • Affiliations:

  • Department of Computing Science, University of Newcastle, Claremont Tower, Newcastle upon Tyne NE1 7RU, UK. l.j.steggles@ncl.ac.uk;Ludwig-Maximilians-Universität of München, Lehr-und Forschungseinheit für Programmierung und Software Technik, Oettingenstrasse 67, D-80538 München, Germany. kosiucze@informati ...

  • Venue:
  • Automated Software Engineering
  • Year:
  • 2000

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Abstract

SDL is an industrial standard formal description techniquefor telecommunication systems. However, despite its wide spread useand industrial importance it lacks at present an adequate formalsemantics integrating its static, dynamic, and real-time aspects.Timed Rewriting Logic (TRL) is a new timed variant of Rewriting Logic(RL), an algebraic formalism which allows the dynamic behaviour ofsystems to be axiomatised using rewrite rules. In this paper wedefine a new formal semantics for SDL using TRL which captures in anatural way the hierarchical structure, and the static and dynamicaspects of an SDL system. The semantics demonstrates the expressivepower, versatility and automation advantages of using TRL. Weconsider how our new semantics can be used to simulate and reasonabout SDL specifications and in particular, we present an equivalencetheorem that allows a wide range of TRL specifications to beimplemented using RL and its associated tool support.